1. Field of the Invention
The present invention relates generally to a method of fabricating semiconductor devices. More particularly, the present invention relates to a method of fabricating a fin field-effect-transistor (Fin-FET) device with better gate height control and ILD (inter-layer dielectric) control.
2. Description of the Prior Art
Continuing advances in semiconductor manufacturing processes have resulted in semiconductor devices with finer features and higher degrees of integration. As the size of the integrated circuit (IC) devices continues to scale down, the polysilicon gate and the silicon dioxide insulating layer of a metal-oxide-semiconductor field effect transistor (MOSFET) structure have confronted with the physical limits of the materials themselves. To meet the demands of scalability, it is necessary to incorporate high-k metal gate (HK/MG) process.
Typically, two main integration options are used: gate-first (often referred to as MIPS, metal inserted poly-silicon) and gate-last (also called RMG, replacement metal gate). The terminology “first” and “last” refers to whether the metal electrode is deposited before or after the high temperature activation anneal of the flow. The RMG process typically involves a bulk tungsten filling process in a gate trench to form a low-resistance metal layer in the composite metal gate structure.
The scaling down of the feature sizes has also increased the complexity of processing and manufacturing ICs. For example, the prior art method for forming a three dimensional transistor such as a fin field-effect transistor (FinFET) usually requires the deposition of Flowable CVD oxide and HDPCVD oxide, followed by at least three CMP steps: FOXCMP (FCVD oxide CMP), HDPCMP (HDPCVD oxide CMP), and POPCMP (Poly Opening Polish CMP), which lead to worse dishing effect and gate height control issue. Therefore, there is a need in this technical field to provide an improved method of fabricating a semiconductor structure such as a FinFET device without such issues.